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68 lines
2.1 KiB
XML
68 lines
2.1 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE entry SYSTEM "SamplesInfo.dtd">
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<entry>
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<name>threadFenceReduction</name>
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<description><![CDATA[This sample shows how to perform a reduction operation on an array of values using the thread Fence intrinsic to produce a single value in a single kernel (as opposed to two or more kernel calls as shown in the "reduction" CUDA Sample). Single-pass reduction requires global atomic instructions (Compute Capability 2.0 or later) and the _threadfence() intrinsic (CUDA 2.2 or later).]]></description>
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<devicecompilation>whole</devicecompilation>
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<includepaths>
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<path>./</path>
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<path>../</path>
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<path>../../Common</path>
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</includepaths>
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<keyconcepts>
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<concept level="basic">Cooperative Groups</concept>
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<concept level="advanced">Data-Parallel Algorithms</concept>
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<concept level="advanced">Performance Strategies</concept>
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</keyconcepts>
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<keywords>
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<keyword>reduction</keyword>
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</keywords>
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<libraries>
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</libraries>
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<librarypaths>
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</librarypaths>
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<nsight_eclipse>true</nsight_eclipse>
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<primary_file>threadFenceReduction.cu</primary_file>
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<scopes>
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<scope>1:CUDA Advanced Topics</scope>
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<scope>1:Data-Parallel Algorithms</scope>
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<scope>1:Performance Strategies</scope>
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</scopes>
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<sm-arch>sm35</sm-arch>
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<sm-arch>sm37</sm-arch>
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<sm-arch>sm50</sm-arch>
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<sm-arch>sm52</sm-arch>
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<sm-arch>sm60</sm-arch>
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<sm-arch>sm61</sm-arch>
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<sm-arch>sm70</sm-arch>
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<sm-arch>sm72</sm-arch>
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<sm-arch>sm75</sm-arch>
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<sm-arch>sm80</sm-arch>
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<sm-arch>sm86</sm-arch>
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<supported_envs>
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<env>
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<arch>x86_64</arch>
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<platform>linux</platform>
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</env>
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<env>
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<platform>windows7</platform>
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</env>
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<env>
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<arch>x86_64</arch>
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<platform>macosx</platform>
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</env>
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<env>
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<arch>arm</arch>
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</env>
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<env>
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<arch>ppc64le</arch>
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<platform>linux</platform>
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</env>
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</supported_envs>
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<supported_sm_architectures>
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<include>all</include>
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</supported_sm_architectures>
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<title>threadFenceReduction</title>
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<type>exe</type>
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</entry>
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