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656 lines
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656 lines
24 KiB
Plaintext
/* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of NVIDIA CORPORATION nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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// CUDA sample demonstrating a integer GEMM computation using the Warp Matrix
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// Multiply and Accumulate API.
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// In this program, the compute_gemm kernel computes the result of a matrix
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// multiplication and addition: D = alpha * A * B + beta * C. The dimensions of
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// both C and D matrices are M_GLOBAL x N_GLOBAL. The A matrix is M_GLOBAL x
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// K_GLOBAL (row-major), the B matrix is K_GLOBAL x N_GLOBAL (column-major). In
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// that kernel, each CTA computes one 128 x 128 tile of the resulting matrix per
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// iteration. When the tile is computed, the CTA stores it to the global memory
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// and begins a new iteration, selecting a new 128 x 128 tile to compute.
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// Each CTA consists of eight warps. For the 128 x 128 tile, each warp computes
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// eight 16 x 16 subtiles, organized in a 2 x 4 two-dimensional array. Warps
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// compute the 16 x 16 subtiles using nvcuda::wmma::mma_sync operations by
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// moving through the K_GLOBAL dimension of the A and B matrices and
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// accumulating the intermediate result in the local thread state.
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// There are a number of simple optimizations used in the algorithm:
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// - The CTA copies the 128 x 128 tile of the C matrix from the global memory to
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// shared memory. After that is done, each warp loads the C matrix fragments
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// from shared memory, thus avoiding a random global memory access.
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// - On each internal iteration, the CTA copies a portion of the A and B
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// matrices from
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// global memory to shared memory. After that, all warps in the CTA reuse the
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// A and B data from shared memory, thus reducing the number of data copies
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// from global memory.
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// - The portions of the A and B matrices are stored in shared memory with an
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// additional
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// padding (skew) to reduce the number of shared memory access bank conflicts.
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// (See a detailed explanation near the SKEW_HALF macro definition.)
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// - When the CTA finishes computing the tiles of the resulting matrix, each
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// warp stores
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// its subtiles to shared memory. The CTA then copies the shared memory
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// contents to global memory, again avoiding redundant random global memory
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// accesses.
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// - Note that the CTA tile size is chosen to maximize the GPU register
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// utilization,
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// but carefully enough to avoid local memory use.
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#include <assert.h>
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#include <cuda.h>
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#include <mma.h>
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#include <stdio.h>
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// helper functions and utilities to work with CUDA
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#include <helper_cuda.h>
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#include <helper_functions.h>
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// Externally configurable parameters.
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#ifndef CPU_DEBUG
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// Set this to 1 to verify the correctness of the GPU-computed matrix.
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#define CPU_DEBUG 0
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#endif
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#ifndef SHARED_MEMORY_LIMIT_64K
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// Set this to 0 to use more than 64 Kb of shared memory to cache data, to
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// improve the performance of the computations on GPU.
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// Note that you need a GPU that can have more than 64 Kb of shared memory
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// per multiprocessor.
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#define SHARED_MEMORY_LIMIT_64K 1
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#endif
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// GPU configuration.
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#define WARP_SIZE 32
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// MMA matrix tile dimensions.
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#define M 16
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#define N 16
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#define K 16
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#define WMMA_M 16
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#define WMMA_N 16
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#define WMMA_K 16
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// GEMM configuration.
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#define M_TILES 256
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#define N_TILES 256
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#define K_TILES 256
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#define M_GLOBAL (M * M_TILES)
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#define N_GLOBAL (N * N_TILES)
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#define K_GLOBAL (K * K_TILES)
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#define C_LAYOUT wmma::mem_row_major
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// Implementation constants.
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#define WARPS_PER_BLOCK 8
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#define THREADS_PER_BLOCK (WARP_SIZE * WARPS_PER_BLOCK)
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#if SHARED_MEMORY_LIMIT_64K
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// With only 64 Kb shared memory available, we can fit two 8-tile chunks of
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// the A and B matrix data, that are 16 * 16 * 8 * 8 * 2 = 32 Kb each
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// (i.e. two 8x8 arrays of tiles of 16x16 uint8_t-typed elements per CTA).
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// But we cannot account the 8 Kb total skew overhead, without which the
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// performance would be severely impacted. So we choose to reduce the chunk size
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// in half, i.e. the amount of A and B matrix data we cache in shared memory.
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// Accordingly, this doubles the number of outer iterations across the global K
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// dimension, which only slightly impacts the performance.
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#define CHUNK_K 8
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#else
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#define CHUNK_K 16
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#endif
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#define CHUNK_LINE_BYTES (CHUNK_K * K * sizeof(uint8_t))
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#define WARP_COPY_BYTES (WARP_SIZE * sizeof(int4))
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#define CHUNK_COPY_LINES_PER_WARP (WARP_COPY_BYTES / CHUNK_LINE_BYTES)
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#define CHUNK_COPY_LINE_LANES (WARP_SIZE / CHUNK_COPY_LINES_PER_WARP)
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#define BLOCK_ROW_WARPS 2
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#define BLOCK_COL_WARPS 4
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#define WARP_ROW_TILES 4
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#define WARP_COL_TILES 2
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#define BLOCK_ROW_TILES (WARP_ROW_TILES * BLOCK_ROW_WARPS)
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#define BLOCK_COL_TILES (WARP_COL_TILES * BLOCK_COL_WARPS)
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#define GLOBAL_MEM_STRIDE N_GLOBAL
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#define SHMEM_STRIDE (N * BLOCK_ROW_TILES)
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#define SHMEM_OFFSET (N * WARP_ROW_TILES)
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// The macro below is used to shift rows of the A matrix and columns of the B
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// matrix in shared memory to minimize possible bank conflicts. Before
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// performing the nvcuda::wmma::mma_sync operation, the warp must load the
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// matrix data using the nvcuda::wmma::load_matrix_sync operation. Although the
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// memory access pattern is not specified for that function, each lane in the
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// warp can read one or multiple matrix elements from different matrix rows or
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// columns. For shared memory, such access can result in bank conflicts if
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// different rows / columns of the matrix map to the same bank. By shifting each
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// row and column by a few bytes, we make sure that they map to different banks,
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// thus reducing the number of possible bank conflicts. The number of 32
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// one-byte "uint8_t" elements is chosen as the minimum possible shift because
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// we must keep each row and column 256-bit aligned, as required by
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// nvcuda::wmma::load_matrix_sync.
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#define SKEW_UINT8 32
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#define checkKernelErrors(expr) \
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do { \
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expr; \
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\
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cudaError_t __err = cudaGetLastError(); \
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if (__err != cudaSuccess) { \
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printf("Line %d: '%s' failed: %s\n", __LINE__, #expr, \
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cudaGetErrorString(__err)); \
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abort(); \
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} \
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} while (0)
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using namespace nvcuda;
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__host__ void init_host_matrices(uint8_t *a, uint8_t *b, int *c) {
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for (int i = 0; i < M_GLOBAL; i++) {
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for (int j = 0; j < K_GLOBAL; j++) {
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a[i * K_GLOBAL + j] = (uint8_t)(rand() % 3);
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}
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}
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for (int i = 0; i < N_GLOBAL; i++) {
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for (int j = 0; j < K_GLOBAL; j++) {
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b[i * K_GLOBAL + j] = (uint8_t)(rand() % 3);
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}
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}
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for (int t = 0; t < M_GLOBAL * N_GLOBAL; t++) {
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c[t] = (rand() % 3);
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}
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}
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__global__ void compute_gemm_imma(const uint8_t *A, const uint8_t *B,
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const int *C, int *D, int alpha, int beta) {
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extern __shared__ uint8_t shmem[][CHUNK_K * K + SKEW_UINT8];
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// Warp and lane identification.
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const unsigned int warpId = threadIdx.x / WARP_SIZE;
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const unsigned int laneId = threadIdx.x % WARP_SIZE;
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// Offset in shared memory from which the B matrix is stored.
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const size_t shmem_idx_b_off = BLOCK_COL_TILES * M;
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// This pointer is used to access the C and D matrix tiles this warp computes.
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int *shmem_warp_tile_ptr = (int *)&shmem[0][0] +
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(warpId / 2) * SHMEM_STRIDE * K * 2 +
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(warpId % 2) * SHMEM_OFFSET;
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// This pointer is used to stream the C and D matrices block-wide tile to and
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// from shared memory.
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int *shmem_warp_stream_ptr = (int *)&shmem[0][0] + warpId * SHMEM_STRIDE * K;
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// Adjust the beta scaler, as it'll be multiplied by alpha at the end of
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// each tile computation. Technically this is not generally correct (may
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// result in a loss of precision). Zero still needs to be specially handled
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// though.
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beta /= alpha;
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// Each CTA slides along the 128 x 128 tiles from the top left corner of the
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// matrix to the right and down, and selects the next tile to compute. Once
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// there's no such tile, all warps in this CTA exit.
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for (unsigned int block_pos = blockIdx.x;; block_pos += gridDim.x) {
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const unsigned int block_tile_i =
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((block_pos * BLOCK_ROW_TILES) / N_TILES) * (BLOCK_COL_TILES);
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const unsigned int block_tile_j = (block_pos * BLOCK_COL_TILES) % N_TILES;
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// Stop when there are no more D matrix tiles to compute in this CTA.
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if (block_tile_i >= M_TILES) {
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break;
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}
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// This warp's pointer to the C matrix data to copy memory from to shared
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// memory.
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const size_t gmem_idx =
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(block_tile_i + warpId) * M * GLOBAL_MEM_STRIDE + block_tile_j * N;
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const int *src_gmem_warp_stream_ptr = &C[gmem_idx];
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// Stream multiple C tiles to shared memory.
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#pragma unroll
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for (int i = 0; i < K; i++) {
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typedef int4 copy_t;
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*((copy_t *)(shmem_warp_stream_ptr + SHMEM_STRIDE * i) + laneId) =
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*((copy_t *)(src_gmem_warp_stream_ptr + GLOBAL_MEM_STRIDE * i) +
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laneId);
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}
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__syncthreads();
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// These fragments will accumulate the result of A and B matrix fragment
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// multiplications along the K_GLOBAL dimension.
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wmma::fragment<wmma::accumulator, M, N, K, int> c[WARP_COL_TILES]
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[WARP_ROW_TILES];
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// Load the C matrix tiles into fragments from shared memory.
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#pragma unroll
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for (int i = 0; i < WARP_COL_TILES; i++) {
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#pragma unroll
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for (int j = 0; j < WARP_ROW_TILES; j++) {
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const int *tile_ptr =
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shmem_warp_tile_ptr + i * SHMEM_STRIDE * K + j * N;
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wmma::load_matrix_sync(c[i][j], tile_ptr, SHMEM_STRIDE, C_LAYOUT);
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}
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}
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__syncthreads();
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// Scale the C matrix.
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#pragma unroll
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for (int i = 0; i < WARP_COL_TILES; i++) {
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#pragma unroll
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for (int j = 0; j < WARP_ROW_TILES; j++) {
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#pragma unroll
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for (int t = 0; t < c[i][j].num_elements; t++) {
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c[i][j].x[t] *= beta;
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}
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}
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}
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// Select what warp copies what matrix to shared memory.
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// Warps 0-3 copy the A matrix, warps 4-7 copy the B matrix.
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const uint8_t *warp_ptr = (warpId < 4) ? (&A[block_tile_i * M * K_GLOBAL] +
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M * K_GLOBAL * (warpId % 4) * 2)
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: (&B[block_tile_j * N * K_GLOBAL] +
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N * K_GLOBAL * (warpId % 4) * 2);
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// Go through the global K dimension by a fixed step at a time.
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#pragma unroll
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for (int tile_k = 0; tile_k < K_TILES; tile_k += CHUNK_K) {
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// Copy slices of the A and B matrices to shared memory.
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// The first half of the warps in the CTA copy the A matrix, the rest copy
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// the B matrix.
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size_t shmem_idx =
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warpId < (WARPS_PER_BLOCK / 2)
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? (M * (warpId % (WARPS_PER_BLOCK / 2)) * 2)
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: (N * (warpId % (WARPS_PER_BLOCK / 2)) * 2 + shmem_idx_b_off);
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// First half of the warp copies the first row / column of the matrix,
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// the second half of the warp copies the next.
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int4 *lane_ptr = (int4 *)(warp_ptr + tile_k * K +
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(laneId / CHUNK_COPY_LINE_LANES) * K_GLOBAL) +
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(laneId % CHUNK_COPY_LINE_LANES);
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// Shift the second half of the warp to the next row / column in the
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// shared memory.
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shmem_idx += laneId / CHUNK_COPY_LINE_LANES;
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#pragma unroll
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for (int i = 0; i < ((WARP_SIZE / 2) / CHUNK_COPY_LINES_PER_WARP) * 2;
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i++) {
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// Copy 16 bytes at once in each lane.
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*((int4 *)&shmem[shmem_idx][0] + (laneId % CHUNK_COPY_LINE_LANES)) =
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*lane_ptr;
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// Advance the global memory pointer and the shared memory index.
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lane_ptr = (int4 *)((uint8_t *)lane_ptr +
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K_GLOBAL * CHUNK_COPY_LINES_PER_WARP);
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shmem_idx += CHUNK_COPY_LINES_PER_WARP;
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}
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__syncthreads();
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// Compute a grid of C matrix tiles in each warp.
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#pragma unroll
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for (int k_step = 0; k_step < CHUNK_K; k_step++) {
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wmma::fragment<wmma::matrix_a, M, N, K, uint8_t, wmma::row_major>
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a[WARP_COL_TILES];
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wmma::fragment<wmma::matrix_b, M, N, K, uint8_t, wmma::col_major>
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b[WARP_ROW_TILES];
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#pragma unroll
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for (int i = 0; i < WARP_COL_TILES; i++) {
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size_t shmem_idx_a = (warpId / 2) * M * 2 + (i * M);
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const uint8_t *tile_ptr = &shmem[shmem_idx_a][k_step * K];
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wmma::load_matrix_sync(a[i], tile_ptr, K * CHUNK_K + SKEW_UINT8);
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#pragma unroll
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for (int j = 0; j < WARP_ROW_TILES; j++) {
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if (i == 0) {
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// Load the B matrix fragment once, because it is going to be
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// reused against the other A matrix fragments.
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size_t shmem_idx_b = shmem_idx_b_off +
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(WARP_ROW_TILES * N) * (warpId % 2) +
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(j * N);
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const uint8_t *tile_ptr = &shmem[shmem_idx_b][k_step * K];
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wmma::load_matrix_sync(b[j], tile_ptr, K * CHUNK_K + SKEW_UINT8);
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}
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wmma::mma_sync(c[i][j], a[i], b[j], c[i][j]);
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}
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}
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}
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__syncthreads();
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}
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// Store the D fragments to shared memory.
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#pragma unroll
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for (int i = 0; i < WARP_COL_TILES; i++) {
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#pragma unroll
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for (int j = 0; j < WARP_ROW_TILES; j++) {
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#pragma unroll
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// Uniform, point-wise transformations of ALL fragment elements by ALL
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// threads in the warp are well-defined even though element indices
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// within fragment storage are not defined.
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for (int t = 0; t < c[i][j].num_elements; t++) c[i][j].x[t] *= alpha;
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int *tile_ptr = shmem_warp_tile_ptr + i * SHMEM_STRIDE * K + j * N;
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wmma::store_matrix_sync(tile_ptr, c[i][j], SHMEM_STRIDE, C_LAYOUT);
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}
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}
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__syncthreads();
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// Now that shared memory contains all the D tiles, stream them to global
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// memory.
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int *dst_gmem_warp_stream_ptr = &D[gmem_idx];
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#pragma unroll
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for (int i = 0; i < K; i++) {
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*((int4 *)(dst_gmem_warp_stream_ptr + GLOBAL_MEM_STRIDE * i) + laneId) =
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*((int4 *)(shmem_warp_stream_ptr + SHMEM_STRIDE * i) + laneId);
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}
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__syncthreads();
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}
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}
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// Performs an MxNxK GEMM (C=alpha*A*B + beta*C) assuming:
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// 1) Matrices are packed in memory.
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// 2) M, N and K are multiples of 16.
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// 3) Neither A nor B are transposed.
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// Note: This is a less performant version of the compute_gemm_imma kernel. It
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// is designed for
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// demonstration purposes only to show the CUDA WMMA API use without
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// relying on availability of the shared memory.
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__global__ void simple_wmma_gemm_imma(const uint8_t *a, const uint8_t *b,
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const int *c, int *d, int m_ld, int n_ld,
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int k_ld, int alpha, int beta) {
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// Leading dimensions. Packed with no transpositions.
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int lda = m_ld;
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int ldb = k_ld;
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int ldc = n_ld;
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// Tile using a 2D grid
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int warpM = (blockIdx.x * blockDim.x + threadIdx.x) / warpSize;
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int warpN = (blockIdx.y * blockDim.y + threadIdx.y);
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// Declare the fragments
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wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, uint8_t,
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wmma::row_major>
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a_frag;
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wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, uint8_t,
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wmma::col_major>
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b_frag;
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wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, int> acc_frag;
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wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, int> c_frag;
|
|
|
|
wmma::fill_fragment(acc_frag, 0.0f);
|
|
|
|
// Loop over k
|
|
for (int i = 0; i < k_ld; i += WMMA_K) {
|
|
int aCol = i;
|
|
int aRow = warpM * WMMA_M;
|
|
|
|
int bCol = i;
|
|
int bRow = warpN * WMMA_N;
|
|
|
|
// Bounds checking
|
|
if (aRow < m_ld && aCol < k_ld && bRow < k_ld && bCol < n_ld) {
|
|
// Load the inputs
|
|
wmma::load_matrix_sync(a_frag, a + aCol + aRow * lda, lda);
|
|
wmma::load_matrix_sync(b_frag, b + bCol + bRow * ldb, ldb);
|
|
|
|
// Perform the matrix multiplication
|
|
wmma::mma_sync(acc_frag, a_frag, b_frag, acc_frag);
|
|
}
|
|
}
|
|
|
|
// Load in the current value of c, scale it by beta, and add this our result
|
|
// scaled by alpha
|
|
int cCol = warpN * WMMA_N;
|
|
int cRow = warpM * WMMA_M;
|
|
|
|
if (cRow < m_ld && cCol < n_ld) {
|
|
wmma::load_matrix_sync(c_frag, c + cCol + cRow * ldc, ldc,
|
|
wmma::mem_row_major);
|
|
|
|
for (int i = 0; i < c_frag.num_elements; i++) {
|
|
c_frag.x[i] = alpha * acc_frag.x[i] + beta * c_frag.x[i];
|
|
}
|
|
|
|
// Store the output
|
|
wmma::store_matrix_sync(d + cCol + cRow * ldc, c_frag, ldc,
|
|
wmma::mem_row_major);
|
|
}
|
|
}
|
|
|
|
__host__ void matMultiplyOnHost(uint8_t *A, uint8_t *B, int *C, int alpha,
|
|
int beta, int numARows, int numAColumns,
|
|
int numBRows, int numBColumns, int numCRows,
|
|
int numCColumns) {
|
|
for (int i = 0; i < numCRows; i++) {
|
|
for (int j = 0; j < numCColumns; j++) {
|
|
int temp = 0;
|
|
|
|
for (int k = 0; k < numAColumns; k++) {
|
|
temp += A[i * numAColumns + k] * B[j * numBRows + k];
|
|
}
|
|
|
|
C[i * numCColumns + j] = temp * alpha + beta * C[i * numCColumns + j];
|
|
}
|
|
}
|
|
}
|
|
|
|
int main(int argc, char **argv) {
|
|
printf("Initializing...\n");
|
|
|
|
int dev = findCudaDevice(argc, (const char **)argv);
|
|
|
|
cudaDeviceProp deviceProp;
|
|
checkCudaErrors(cudaGetDeviceProperties(&deviceProp, dev));
|
|
|
|
// Tensor cores require a GPU of Volta (SM72) architecture or higher.
|
|
if (deviceProp.major < 7 || (deviceProp.major <= 7 && deviceProp.minor < 2)) {
|
|
printf(
|
|
"immaTensorCoreGemm requires SM 7.2 or higher to use Tensor Cores. "
|
|
"Exiting...\n");
|
|
exit(EXIT_WAIVED);
|
|
}
|
|
|
|
printf("M: %d (%d x %d)\n", M_GLOBAL, M, M_TILES);
|
|
printf("N: %d (%d x %d)\n", N_GLOBAL, N, N_TILES);
|
|
printf("K: %d (%d x %d)\n", K_GLOBAL, K, K_TILES);
|
|
|
|
uint8_t *A_h = NULL;
|
|
uint8_t *B_h = NULL;
|
|
int *C_h = NULL;
|
|
#if CPU_DEBUG
|
|
int *result_hD = NULL;
|
|
int *result_host = NULL;
|
|
#endif
|
|
|
|
A_h = (uint8_t *)malloc(sizeof(uint8_t) * M_GLOBAL * K_GLOBAL);
|
|
B_h = (uint8_t *)malloc(sizeof(uint8_t) * K_GLOBAL * N_GLOBAL);
|
|
C_h = (int *)malloc(sizeof(int) * M_GLOBAL * N_GLOBAL);
|
|
#if CPU_DEBUG
|
|
result_hD = (int *)malloc(sizeof(int) * M_GLOBAL * N_GLOBAL);
|
|
result_host = (int *)malloc(sizeof(int) * M_GLOBAL * N_GLOBAL);
|
|
#endif
|
|
|
|
uint8_t *A = NULL;
|
|
uint8_t *B = NULL;
|
|
int *C = NULL;
|
|
int *D = NULL;
|
|
|
|
checkCudaErrors(
|
|
cudaMalloc(reinterpret_cast<void **>(&A), sizeof(uint8_t) * M_GLOBAL * K_GLOBAL));
|
|
checkCudaErrors(
|
|
cudaMalloc(reinterpret_cast<void **>(&B), sizeof(uint8_t) * N_GLOBAL * K_GLOBAL));
|
|
checkCudaErrors(cudaMalloc(reinterpret_cast<void **>(&C), sizeof(int) * M_GLOBAL * N_GLOBAL));
|
|
checkCudaErrors(cudaMalloc(reinterpret_cast<void **>(&D), sizeof(int) * M_GLOBAL * N_GLOBAL));
|
|
|
|
assert(((unsigned long long)A) % 128 == 0);
|
|
assert(((unsigned long long)B) % 128 == 0);
|
|
assert(((unsigned long long)C) % 128 == 0);
|
|
assert(((unsigned long long)D) % 128 == 0);
|
|
|
|
init_host_matrices(A_h, B_h, C_h);
|
|
|
|
checkCudaErrors(cudaMemcpy(A, A_h, sizeof(uint8_t) * M_GLOBAL * K_GLOBAL,
|
|
cudaMemcpyHostToDevice));
|
|
checkCudaErrors(cudaMemcpy(B, B_h, sizeof(uint8_t) * N_GLOBAL * K_GLOBAL,
|
|
cudaMemcpyHostToDevice));
|
|
checkCudaErrors(cudaMemcpy(C, C_h, sizeof(int) * M_GLOBAL * N_GLOBAL,
|
|
cudaMemcpyHostToDevice));
|
|
checkCudaErrors(cudaMemset(D, 0, sizeof(int) * M_GLOBAL * N_GLOBAL));
|
|
|
|
printf("Preparing data for GPU...\n");
|
|
|
|
assert(((unsigned long long)A) % 128 == 0);
|
|
assert(((unsigned long long)B) % 128 == 0);
|
|
assert(((unsigned long long)C) % 128 == 0);
|
|
assert(((unsigned long long)D) % 128 == 0);
|
|
|
|
enum {
|
|
// Compute the right amount of shared memory to request.
|
|
// We need shared memory to hold per-CTA C and D matrix tiles, and to cache
|
|
// per-CTA chunks
|
|
// of the A and B matrices. Therefore, the right amount to request is the
|
|
// maximum of those
|
|
// two numbers.
|
|
SHMEM_SZ = MAX(sizeof(uint8_t) * (BLOCK_COL_TILES * M) *
|
|
(CHUNK_K * K + SKEW_UINT8) * 2,
|
|
M * (BLOCK_ROW_WARPS * WARP_ROW_TILES) * N *
|
|
(BLOCK_COL_WARPS * WARP_COL_TILES) * sizeof(int))
|
|
};
|
|
|
|
printf("Required shared memory size: %lu Kb\n", SHMEM_SZ / 1024UL);
|
|
|
|
int alpha = 1;
|
|
int beta = 1;
|
|
|
|
cudaEvent_t start, stop;
|
|
|
|
checkCudaErrors(cudaEventCreate(&start));
|
|
checkCudaErrors(cudaEventCreate(&stop));
|
|
checkCudaErrors(cudaEventRecord(start));
|
|
|
|
// If enough shared memory available on the GPU use high performant kernel
|
|
if (deviceProp.sharedMemPerMultiprocessor >= SHMEM_SZ) {
|
|
printf("Computing... using high performance kernel compute_gemm_imma \n");
|
|
|
|
checkCudaErrors(cudaFuncSetAttribute(
|
|
compute_gemm_imma, cudaFuncAttributeMaxDynamicSharedMemorySize,
|
|
SHMEM_SZ));
|
|
checkKernelErrors(
|
|
(compute_gemm_imma<<<deviceProp.multiProcessorCount, THREADS_PER_BLOCK,
|
|
SHMEM_SZ>>>(A, B, C, D, alpha, beta)));
|
|
#if CPU_DEBUG
|
|
checkCudaErrors(cudaMemcpy(result_hD, D, sizeof(int) * M_GLOBAL * N_GLOBAL,
|
|
cudaMemcpyDeviceToHost));
|
|
#endif
|
|
} else {
|
|
dim3 gridDim;
|
|
dim3 blockDim;
|
|
|
|
// blockDim.x must be a multiple of warpSize
|
|
// 128x4 means we have 16 warps and a block computes a 64x64 output tile
|
|
blockDim.x = 128;
|
|
blockDim.y = 4;
|
|
|
|
gridDim.x = (M_GLOBAL + (WMMA_M * blockDim.x / 32 - 1)) /
|
|
(WMMA_M * blockDim.x / 32);
|
|
gridDim.y = (N_GLOBAL + WMMA_N * blockDim.y - 1) / (WMMA_N * blockDim.y);
|
|
|
|
printf("Computing... using simple_wmma_gemm_imma kernel\n");
|
|
simple_wmma_gemm_imma<<<gridDim, blockDim>>>(A, B, C, D, M_GLOBAL, N_GLOBAL,
|
|
K_GLOBAL, alpha, beta);
|
|
#if CPU_DEBUG
|
|
checkCudaErrors(cudaMemcpy(result_hD, D, sizeof(int) * M_GLOBAL * N_GLOBAL,
|
|
cudaMemcpyDeviceToHost));
|
|
#endif
|
|
}
|
|
|
|
checkCudaErrors(cudaEventRecord(stop));
|
|
checkCudaErrors(cudaEventSynchronize(stop));
|
|
|
|
#if CPU_DEBUG
|
|
printf("Verifying correctness of the computations...\n");
|
|
|
|
memcpy(result_host, C_h, sizeof(int) * M_GLOBAL * N_GLOBAL);
|
|
|
|
matMultiplyOnHost(A_h, B_h, result_host, alpha, beta, M_GLOBAL, K_GLOBAL,
|
|
K_GLOBAL, N_GLOBAL, M_GLOBAL, N_GLOBAL);
|
|
|
|
for (int i = 0; i < N_GLOBAL * M_GLOBAL; i++) {
|
|
if (abs(result_hD[i] - result_host[i]) > 0) {
|
|
printf("mismatch i=%d result_hD=%d result_host=%d\n", i, result_hD[i],
|
|
result_host[i]);
|
|
}
|
|
}
|
|
free(result_host);
|
|
free(result_hD);
|
|
#endif
|
|
|
|
float milliseconds = 0;
|
|
|
|
checkCudaErrors(cudaEventElapsedTime(&milliseconds, start, stop));
|
|
|
|
printf("Time: %f ms\n", milliseconds);
|
|
printf("TOPS: %.2f\n", (((double)M_GLOBAL * N_GLOBAL * K_GLOBAL * 2)/(milliseconds/1000.)) / 1e12);
|
|
|
|
free(A_h);
|
|
free(B_h);
|
|
free(C_h);
|
|
checkCudaErrors(cudaFree(reinterpret_cast<void *>(A)));
|
|
checkCudaErrors(cudaFree(reinterpret_cast<void *>(B)));
|
|
checkCudaErrors(cudaFree(reinterpret_cast<void *>(C)));
|
|
checkCudaErrors(cudaFree(reinterpret_cast<void *>(D)));
|
|
|
|
return EXIT_SUCCESS;
|
|
}
|